A typical electronic system may include multiple integrated circuit devices, often referred to as “chips.” In some types of systems, there can be a need to distinguish one chip from another. Even more particularly, it may be desirable to assign a unique chip identification value (chip ID) to each chip in a system. Such an arrangement may be advantageous in testing devices in system, or in network applications, as will be described below. Chip IDs may be “hard-wired” or programmable. Hard-wired chip IDs can be established when a device is manufactured, and so may be set by a manufacturing process or step, and so may not be changed. Programmable chip IDs, as the name implies, may be programmed by a user or other system device or process.
Device identification values may be associated with a particular part of a system, as opposed to a single chip of a system. A well-known hardware identification value is a media access control (MAC) address. A MAC address can be a unique value associated with a particular network device, typically a network adapter. MAC addresses are also known as network hardware addresses or network “physical” addresses. A MAC address can uniquely identify a network device on a network, to thereby enable transfer of data from and to such a device. A MAC address is a 12 digit hexadecimal number having a predetermined format. Such a format may include a manufacturer identifier and a device serial number, and is dictated by predetermined standards.
While a MAC address serves network addressing well, such a value can be cumbersome for applications in systems having fewer components, and/or requiring command execution or more compact chip addressing as it can include 48 bits of data.
Another conventional approach for providing unique chip ID values to chips included in a system can be “pin” addressing. In pin addressing, distinct pins (e.g., conductive leads) of a chip can be tied to high or lower power supply voltages to establish either a “1” or “0” input. Such pins may thus establish a chip address.
A drawback to pin addressing can be increased pin count for a device, as a number of pins would be dedicated chip address pins. Further, pin addressing may complicate the layout of system boards (e.g., modules), or the like, as the number chips ultimately included in a board may not be know at the time a board is manufactured.
Conventional pin addressing schemes for a serial arrangement of chips are known. Such conventional approaches may issue a command, in packet form, that can assign an initial chip ID to a first device in a serial sequence. Each device in the serial sequence may assign a received chip ID value, increment such a value, and then forward the command to the next device in a sequence. In this way, unique chip ID values may be assigned in a system having a serial arrangement of chips.
One particular type of system that can include multiple chips is a search engine system. Search engine systems typically perform a search operation that can compare a search value (e.g., a comparand or key) against a number of other data values. In the event a search value matches a data value, a search result may be considered a “hit” (e.g., match). If a search value does not match any data values, a search result may be considered a “miss” (e.g., no match).
Search engines may take various forms. A search engine may be based on a general-purpose processor and accompanying algorithm that may access a number of memory devices. Such approaches may be undesirably costly when compared to smaller device-oriented approaches, such as a content addressable memory (CAM) based search engine systems.
A CAM based search engine system can typically include a number of CAM devices. A CAM device may include a number of entries, each of which may store a data value, or portion thereof. In a search operation, a comparand (or key) may be compared to multiple entries to see if all, or a portion, of the key matches an entry. After a search operation, a CAM device may give a search result as an output. Typically a search result may provide associated data directly, or provide an “index” value that may be used to retrieve associated data from another device, such as a random access memory.
CAM devices may take a variety of forms. As but a few of the possible examples, a CAM device may be based on particular types of CAM cells. Such cells may include storage circuits integrated with compare circuits. Examples of storage circuits may be static random access memory (SRAM) type cells or dynamic random access memory (DRAM) type cells. Alternate approaches may include random access memories (RAM) arrays, or the like, with separate matching circuits and/or processing circuits.
A CAM based system having multiple branches (e.g., processing paths) is disclosed in commonly owned, co-pending patent application Ser. No. 10/109,364, filed on Mar. 28, 2002, and titled CASCADABLE CONTENT ADDRESSABLE MEMORY (CAM) DEVICE AND ARCHITECTURE, by James et al., the contents of which are incorporated by reference herein. James et al. also discloses a vote circuit within a CAM device that can make a precedence determination from among multiple responses from CAM devices. Such a precedence determination may include comparing a chip field containing a unique value identifying a chip (e.g. a chip ID).
In light of the above, it would be desirable to arrive at some way of assigning unique chip ID values to chips in a system that has a more complex arrangement than a serial sequence.
It would also be desirable to arrive at some way of assigning unique chip ID values for CAM devices in a CAM based search engine system. Further, such an arrangement could be particularly desirable for CAM based search engine systems that may establish precedence or priority among results based on chip ID values.